[Zlib-devel] [0/6][RFC V2 Introduction] Adler32 vectorization

[Jan Seiffert]

Nearly two weeks have passed, so i think it's time for a repost, this
time with more archs!

Changes V1-> V2
* incorporated little fixes
* renamed reduce_4 to reduce_x
* fix reduce_x to handle reduction of up to 64 byte in the NO_DIVIDE +
NO_SHIFT case
* added a 64-Bit pseudo SIMD version
* added Alpha MAX code
* added mips loongson2f + DSP-ASE code

Testing of the x86 code looks good, but i could _really_ need some
testers on the other archs.
(besides x86 & ppc other archs are only compile tested, BTW. does
someone has a ia64 machine?)
Also, some compile testing with your compiler whatever it may be.

Any review welcome, really!
Questions, additions, changes, style nitpicking, flames, anything.

Greetings
Jan